Efficient Reconfigurable Multipliers Based on the Twin-Precision Technique
Licentiatavhandling, 2006

During the last decade of integrated electronic design ever more functionality has been integrated onto the same chip, paving the way for having a whole system on a single chip. The strive for ever more functionality increases the demands on circuit designers that have to provide the foundation for all this functionality. The desire for increased functionality and an associated capability to adapt to changing requirements, has led to the design of reconfigurable architectures. With an increased interest and use of reconfigurable architectures there is a need for flexible and reconfigurable computational units that can meet the demands of high speed, high throughput, low power, and area efficiency. Multiplications are complex to implement and they continue to give designers headaches when trying to efficiently implement multipliers in hardware. Multipliers are therefore interesting to study, when investigating how to design flexible and reconfigurable computational units. In this thesis the results from investigations on flexible multipliers are presented. The new twin-precision technique, which was developed during this work, makes a multiplier able to adapt to different requirements. By adapting to actual multiplication bitwidth using the twin-precision technique, it is possible to save power, increase speed and double computational throughput. The investigations have also led to the conclusion that the long used and popular modified-Booth multiplier is inferior in all aspects to the less complex Baugh-Wooley multiplier. During this work, a VHDL multiplier generator was created and made publicly available.

Reconfigurable

VLSI

Low-Power

Twin-Precision

Multipliers

High-Speed

Författare

Magnus Själander

Chalmers, Data- och informationsteknik, Datorteknik

A Power-Efficient and Versatile Modified-Booth Multiplier

Swedish System-on-Chip Conference,; (2005)

Konferensbidrag (offentliggjort, men ej förlagsutgivet)

Multiplier Reduction Tree with Logarithmic Logic Depth and Regular Connectivity

IEEE Intl Symposium on Circuits and Systems (ISCAS),; (2006)

Paper i proceeding

A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating

IEEE International Symposium on Circuits and Systems,; (2005)p. 1654-7

Paper i proceeding

An Efficient Twin-Precision Multiplier

International Conference on Computer Design (ICCD),; (2004)p. 30-33

Paper i proceeding

Ämneskategorier

Datorteknik

Technical report L - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University: 12L

Mer information

Skapat

2017-10-07