Design principles for synthesizable processor cores
Paper i proceeding, 2012

As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput on FPGA-based processor cores: first, superpipelining enables higher-frequency system clocks, and second, predicated instructions circumvent costly pipeline stalls due to branches. To evaluate their effects, we develop Tinuso, a processor architecture optimized for FPGA implementation. We demonstrate through the use of micro-benchmarks that our principles guide the design of a processor core that improves performance by an average of 38% over a similar Xilinx MicroBlaze configuration.

pipelining

Pipe linings

Computer architecture

Architecture

Field programmable gate arrays (FPGA)

Benchmarking

Processor architectures

Design Principles

Processor cores

FPGA implementations

synthesizable processor core

Embedded software

System clock

FPGA

Embedded computing

predication

Pipeline processing systems

Pipeline stall

FPGA architectures

Författare

P. Schleuniger

Danmarks Tekniske Universitet (DTU)

Sally A McKee

Chalmers, Data- och informationsteknik, Datorteknik

S. Karlsson

Danmarks Tekniske Universitet (DTU)

Lecture Notes in Computer Science

0302-9743 (ISSN)

Vol. 7179 111-122

Ämneskategorier

Data- och informationsvetenskap

DOI

10.1007/978-3-642-28293-5_10

ISBN

978-364228292-8