Active memory controller
Artikel i vetenskaplig tidskrift, 2012

Inability to hide main memory latency has been increasingly limiting the performance of modern processors. The problem is worse in large-scale shared memory systems, where remote memory latencies are hundreds, and soon thousands, of processor cycles. To mitigate this problem, we propose an intelligent memory and cache coherence controller (AMC) that can execute Active Memory Operations (AMOs). AMOs are select operations sent to and executed on the home memory controller of data. AMOs can eliminate a significant number of coherence messages, minimize intranode and internode memory traffic, and create opportunities for parallelism. Our implementation of AMOs is cache-coherent and requires no changes to the processor core or DRAM chips. In this paper, we present the microarchitecture design of AMC, and the programming model of AMOs. We compare AMOs' performance to that of several other memory architectures on a variety of scientific and commercial benchmarks. Through simulation, we show that AMOs offer dramatic performance improvements for an important set of data-intensive operations, e.g., up to 50x faster barriers, 12x faster spinlocks, 8.5x-15x faster stream/array operations, and 3x faster database queries. We also present an analytical model that can predict the performance benefits of using AMOs with decent accuracy. The silicon cost required to support AMOs is less than 1% of the die area of a typical high performance processor, based on a standard cell implementation.

chip

Distributed shared memory

Memory architecture

Interprocessor synchronization

synchronization

support

architectures

Cache coherence

multiprocessors

Författare

Z. Fang

NVIDIA

L. Zhang

Institute of Computing Technology Chinese Academy of Sciences

J. B. Carter

IBM Austin Research Laboratory

Sally A McKee

Chalmers, Data- och informationsteknik, Datorteknik

A. Ibrahim

Advanced Micro Devices, Inc.

M. A. Parker

NVIDIA

X. W. Jiang

Intel Corporation

Journal of Supercomputing

0920-8542 (ISSN) 1573-0484 (eISSN)

Vol. 62 1 510-549

Ämneskategorier

Data- och informationsvetenskap

DOI

10.1007/s11227-011-0735-9