Smart technologies for effective reconfiguration: The FASTER approach
Paper i proceeding, 2012

Current and future computing systems increasingly require that their functionality stays flexible after the system is operational, in order to cope with changing user requirements and improvements in system features, i.e. changing protocols and data-coding standards, evolving demands for support of different user applications, and newly emerging applications in communication, computing and consumer electronics. Therefore, extending the functionality and the lifetime of products requires the addition of new functionality to track and satisfy the customers needs and market and technology trends. Many contemporary products along with the software part incorporate hardware accelerators for reasons of performance and power efficiency. While adaptivity of software is straightforward, adaptation of the hardware to changing requirements constitutes a challenging problem requiring delicate solutions. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform which includes a general purpose processor combined with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design time and at run time, the capabilities of partial dynamic reconfiguration. The goal is that for selected application domains, the FASTER toolchain will be able to reduce the design and verification time of complex reconfigurable systems providing additional novel verification features that are not available in existing tool flows.


M. D. Santambrogio

Politecnico di Milano

Dionisios N. Pnevmatikatos

Idryma Technologias kai Erevnas (FORTH)

Kyprianos D. Papadimitriou

Idryma Technologias kai Erevnas (FORTH)

Christian Pilato

Politecnico di Milano

Georgi Gaydadjiev

Chalmers, Data- och informationsteknik, Datorteknik

D. Stroobandt

Universiteit Gent

T. Davidson

Universiteit Gent

T. Becker

Imperial College London

T. Todman

Imperial College London

W. Luk

Imperial College London

A. Bonetto

Politecnico di Milano

A. Cazzaniga

Politecnico di Milano

G.C. Durelli

Politecnico di Milano

Donatella Sciuto

Politecnico di Milano

ReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings

978-1-4673-2572-1 (ISBN)

Facilitating Analysis and Synthesis Technologies\nfor Effective Reconfiguration (FASTER)

Europeiska kommissionen (EU) (EC/FP7/287804), 2011-09-01 -- 2014-11-30.


Elektroteknik och elektronik





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