FASTER run-time reconfiguration management
Paper i proceeding, 2013

The FASTER project Run-Time System Manager offloads programmers from low-level operations by performing task placement, scheduling, and dynamic FPGA reconfiguration. It also manages device fragmentation, configuration caching, pre-fetching and reuse, bitstream compression, and optimizes the system thermal and power footprints. We propose a micro-reconfiguration aware, configuration content agnostic ISA interface and a technology independent Task Configuration Microcode format targeting Maxeler Data Flow computers and Xilinx XUPV5 platforms. We achieve improved resource utilization with negligible performance overhead. Up to 4Gbps for DMA transfers, and up to 3Gbps for FPGA reconfiguration on Xilinx Virtex-5/6 devices is achieved.

run-time system manager

FPGA

partial reconfiguration

Författare

Catalin Ciobanu

Chalmers, Data- och informationsteknik, Datorteknik

Dionisios N. Pnevmatikatos

Foundation for Research and Technology Hellas (FORTH)

Kyprianos D. Papadimitriou

Foundation for Research and Technology Hellas (FORTH)

Georgi Gaydadjiev

Chalmers, Data- och informationsteknik, Datorteknik

Proceedings of the International Conference on Supercomputing

463-

Facilitating Analysis and Synthesis Technologies\nfor Effective Reconfiguration (FASTER)

Europeiska kommissionen (FP7), 2011-09-01 -- 2014-11-30.

Ämneskategorier

Datorteknik

Datorsystem

Styrkeområden

Informations- och kommunikationsteknik

DOI

10.1145/2464996.2467283

ISBN

978-145032130-3