On DFM Considerations and Assessment for Nanometer SoCs
Doktorsavhandling, 2014

The incredible density of silicon integrated circuits has brought with it unprecedented technological advances. This is made possible through innovations at each incremental technology node. With the layout geometries of circuits approaching the physical limits of an atom, innovative enablers in manufacturing are scarce; and when they exist, increasingly expensive and/or difficult to implement. This has led to the discipline of Design for Manufacturability (DFM) becoming a mandatory consideration in the design and implementation of electronic systems. In the nanometer era, regularity has been used extensively to combat layout issues that make the implementation of electronic systems challenging. The first part of this thesis presents a semi-custom methodology to implement layouts for datapath elements that exhibit netlist regularity. Here a novel methodology, using a domain-specific, low-level, layout-aware hardware description language, Wired, is used to create netlists for physical implementations of datapath elements such as column compression multipliers and logarithmic shifters. The netlist regularity is preserved during physical design resulting in highly regular, area efficient, yet Design Rule Check (DRC) compliant implementations. In the second part of this thesis, the assessment of manufacturability is presented. DFM tools integrated into the traditional full-custom design environment are used to enable this. This assessment is carried out from the perspective of creating manufacturable nanometer standard-cell libraries. The metric used to assess manufacturability is Critical Feature Analysis (CFA). Counter intuitive trends indicating better manufacturability of standard cells with less regular geometries are showcased. DFM assessment extending the earlier work, and carried out on implementations of the ISCAS ’89 benchmark circuits, show similar results in spite of the fact that raw implementation metrics indicate otherwise. As a final contribution, a simple model to enable early assessment of design manufacturability in System-on-Chips (SoCs) is presented. The model which is based largely on data available from the physical implementation of the design, is demonstrated on a processor implementation including a L1-cache subsystem. Various implementation aspects like floorplan and Intellectual Property (IP) inclusion are investigated in the early assessment of the DFM metric.

Multipliers

CMOS

Shifters

DFM

ASIC

SoC

Regularity

Processor

ED
Opponent: Prof. Rouwaida Kanj, Department of Electrical and Computer Engineering, American University of Beirut, Lebanon

Författare

KASYAB PARMESH SUBRAMANIYAN

Chalmers, Data- och informationsteknik, Datorteknik

Generation and Exploration of Layouts for Area-Efficient Barrel Shifters

Proceedings of IEEE Computer Society Annual Symp. on VLSI (ISVLSI),; (2010)p. 454-455

Paper i proceeding

On Regularity and Integrated DFM Metrics

4th Asia Symposium on Quality Electronic Design (ASQED), Malaysia, July 10-11, 2012,; (2012)p. 211-218

Paper i proceeding

Manufacturable Nanometer Designs using Standard Cells with Regular Layout

Proceedings - International Symposium on Quality Electronic Design, ISQED,; (2013)p. 398-405

Paper i proceeding

Layout Exploration of Geometrically Accurate Arithmetic Circuits

Proceedings of IEEE International Conference of Electronics, Circuits and Systems,; (2009)

Paper i proceeding

Styrkeområden

Informations- och kommunikationsteknik

Ämneskategorier

Inbäddad systemteknik

Datorsystem

Annan elektroteknik och elektronik

ISBN

978-91-7597-037-0

Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie

ED

Opponent: Prof. Rouwaida Kanj, Department of Electrical and Computer Engineering, American University of Beirut, Lebanon