Towards 3D Integration of Carbon Based Electronics
Carbon-based nanomaterials such as carbon nanotubes (CNTs) and graphene, which possess superior electrical, thermal and mechanical properties, have been proposed as alternative materials for future electronics. The proposed applications span from the device level, replacing silicon-based transistors, with single-walled carbon nanotubes (SWCNTs) or graphene, to packaging level using multi-walled carbon nanotubes (MWCNTs) for interconnects. To further exploit the potential of carbon-based electronics in electronic packaging, a novel 3D all carbon based electronic system is targeted in this thesis. In order to achieve the goal of a 3D carbon based electronic system, this thesis addresses some of the technical issues including material synthesis, process compatibility and system integration.
First of all, the synthesis of horizontally-aligned SWCNTs (HA-SWCNTs), vertically-aligned MWCNTs (VA-MWCNTs) and graphene were investigated for material preparation. Especially, growth of HA-SWCNTs on a ST-cut quartz substrate was the first time demonstrated in ac low pressure cold-wall CVD with acetylene as a carbon precursor. In addition, the catalyst engineering of MWCNTs in a hexagonal pattern was performed to achieve high aspect ratio MWCNT bundles for through-silicon-via (TSV) interconnects. The transfer of CNTs and graphene was conducted to circumvent material synthesis incompatibilities with current semiconductor and packaging processes. In particular, tape-assisted transfer of MWCNT bundles for TSVs has been proposed and experimentally demonstrated to increase the yield and efficiency. After the transfer of VA-MWCNT bundle into the via, different polymers were used for filling the gap between the VA-MWCNT bundle and the side-walls of the via, and their performance was investigated and compared. In parallel, attempts were made to stack VA-MWCNT filled TSVs, with and without using isotropic conductive adhesive. Electrical characterization was carried out at each step of the fabrication process.
horizontally aligned SWCNTs
through silicon via