Glitch-Conscious Low-Power Design of Arithmetic Circuits
Paper i proceeding, 2004

Glitches are common in arithmetic circuits, especially in large multipliers where they often represent the major part of transitions. With the aim to provide a judicious glitch-reduction strategy, we extract and study the relation between generated and propagated glitches for three different arithmetic blocks. We show that the number of propagated glitches is far bigger than those generated regardless of circuit type, supply voltage, and threshold voltage. In contrast to existing glitch-reduction strategies we propose to focus also on the glitch propagation mechanism. It is shown how the inverting property of adder cells can be harnessed to reduce propagation of glitches and thus the overall power dissipation.

Författare

Henrik Eriksson

Chalmers, Institutionen för datorteknik, Integrerade elektroniksystem

Per Larsson-Edefors

Chalmers, Institutionen för datorteknik, Integrerade elektroniksystem

2004 IEEE International Symposium on Cirquits and Systems - Proceedings; Vancouver, BC; Canada; 23 May 2004 through 26 May 2004

0271-4310 (ISSN)

Vol. 2 II281-II284

Ämneskategorier

Data- och informationsvetenskap

DOI

10.1109/ISCAS.2004.1329263