Bit-flip aware control-flow error detection
Paper i proceeding, 2015
Recent increase of transient fault rates has made processor reliability a major concern. Moreover performance improvements are required for many of today's embedded systems. At the same time software implemented fault detection remains the only option for off-the-shelf processors. Software methods, however, introduce significant performance overheads due to the additional instructions required for the detection. A good observation is that often code segments not susceptible to faults are protected. In this paper we propose a technique for systematic analysis of the bit-flip effects on the program controlflow in order to identify only those locations susceptible to controlflow errors and hence minimize the number of fault detection assertions. We instrument the code with minimal overhead, while maintaining high fault coverage level. Our experiments show that using the result of our bit-flip analysis and limiting the code instrumentation to only the susceptible locations releases 28.9% (on average) of the memory while the level of fault coverage remains the same as with full instrumentation.