3D Integration of Carbon Based Electronics
Carbon-based nanomaterials such as carbon nanotubes (CNTs) and graphene, which possess superior electrical, thermal and mechanical properties, have been proposed as alternative materials for future electronics. The proposed applications span from the device level, replacing silicon-based transistors, with single-walled carbon nanotubes (SWCNTs) or graphene, to packaging level using multi-walled carbon nanotubes (MWCNTs) for interconnects. To further exploit the potential of carbon-based electronics in electronic packaging, a novel 3D carbon based electronic system is targeted in this thesis. In order to achieve the goal of a 3D carbon based electronic system, this thesis addresses some of the technical issues including material synthesis, process compatibility and system integration.
First of all, the chemical vapor deposition (CVD) synthesis of horizontally-aligned SWCNTs (HA-SWCNTs), vertically-aligned MWCNTs (VA-MWCNTs) and bilayer graphene were investigated for material preparation. For the HA-SWCNTs on the ST-cut quartz substrate, it has been found that adding a top heater is critical for synthesis of high-quality HA-SWCNTs in a cold-wall reactor. The catalyst engineering of MWCNTs in a hexagonal pattern was performed to achieve high aspect ratio MWCNT bundles for through-silicon-via (TSV) interconnects. In addition, a nucleation activity model has been proposed as an explanation for the fast and controllable synthesis of bilayer graphene on a copper foil in the cold wall CVD.
The transfer of CNTs and graphene was conducted to circumvent material synthesis incompatibilities with current semiconductor and packaging processes. The PET frame was utilized to ease the HA-SWCNTs transfer during the transportation. In particular, tape-assisted transfer of MWCNT bundles for TSVs has been proposed and experimentally demonstrated to increase the yield and efficiency. After the transfer of VA-MWCNT bundle into the via, different polymers were used for filling the gap between the VA-MWCNT bundle and the side-walls of the via, and their performance was investigated and compared. In addition, a double densification process has been developed to overcome the tilting issue of the high aspect ratio VA-MWCNTs bundles for the TSV interconnect. For bubbling transfer of graphene, a consolidation polydimethylsiloxane (PDMS) layer was added on top of polymathic methacrylate (PMMA) layer in order to avoid the cracks caused by bubbles.
In order to solve the high resistivity issue of pure VA-MWCNTs filled TSV interconnects, a novel CNT-Cu nanocomposite has been developed. This composite material consisted of high aspect ratios, VA-MWCNTs deposited and coated by Cu, and exhibited the same order of magnitude resistivity as Cu, but with a similar thermal expansion performance to silicon. In parallel, attempts were made to stack pure VA-MWCNT filled TSVs and CNT-Cu nanocomposite filled TSV. In the end, a via-last based process for 3D integration was proposed and demonstrated. Electrical characterization was carried out at each step of the 3D integration process.