A GPU Register File using Static Data Compression
Paper i proceeding, 2020

GPUs rely on large register files to unlock thread-level parallelism for high throughput. Unfortunately, large register files are power hungry, making it important to seek for new approaches to improve their utilization.

This paper introduces a new register file organization for efficient register-packing of narrow integer and floating-point operands designed to leverage on advances in static analysis. We show that the hardware/software co-designed register file organization yields a performance improvement of up to 79%, and 18.6%, on average, at a modest output-quality degradation.

Approximation

Microarchitecture

Data compaction and compression

Graphics processors

Författare

Alexandra Angerd

Chalmers, Data- och informationsteknik, Datorteknik, Computer Systems

Erik Sintorn

Chalmers, Data- och informationsteknik, Datorteknik, Real-time and Computer Graphics Systems

Per Stenström

Chalmers, Data- och informationsteknik, Datorteknik

ICPP ’20: 49th International Conference on Parallel Processing - ICPP

59

ICPP ’20: 49th International Conference on Parallel Processing - ICPP
Edmonton, Canada,

ACE: Approximativa algoritmer och datorsystem

Vetenskapsrådet (VR), 2015-01-01 -- 2018-12-31.

Ämneskategorier

Datorteknik

Programvaruteknik

Datorsystem

Styrkeområden

Informations- och kommunikationsteknik

DOI

10.1145/3404397

Mer information

Skapat

2020-08-10