Exploration of Short Floating-Point Numbers for Hardware-Friendly Digital Predistortion

Paper i proceeding, 2025

Digital predistortion (DPD) is used to reduce nonlinear and memory effects in power amplifiers (PAs). Practical DPD algorithms use variants of Volterra series by opportunistically removing terms to reduce hardware complexity with minimal loss in linearization performance. Although current DPD algorithms can reduce the number of computations in terms of floating-point operations, precision requirements have not been analyzed in depth. With the motivation to reduce hardware complexity, many shorter floating-point formats have recently emerged in response to new application domains, such as machine learning. To study the trade-off between linearization performance and floating-point dynamic range and precision, we implement the basis-propagating selection (BAPS) model in digital hardware. We consider two use-case scenarios for PA models with different memory effects, and find that the requirements on exponent and mantissa resolution can be significantly relaxed from a default single-precision 32-bit format, without any substantial loss in linearization performance.