DSP Hardware Tradeoffs for Digital Predistortion based on Pruned Volterra Series

Paper i proceeding, 2025

This paper presents an investigation into the hardware implementation of a pruned Volterra series based predistorter using floating-point arithmetic. Reduced-complexity pruned Volterra series have been shown to deliver good linearization performance for Digital Predistortion (DPD) in RF Power Amplifiers (PAs). However, this performance has been demonstrated mostly in software applications such as Matlab. In contrast, we explore DSP hardware design tradeoffs where we balance system performance and DPD power consumption. Our investigation is centered on the BAsis Propagating Selection (BAPS) algorithm that has been shown to deliver better performance compared to other pruned Volterra algorithms, such as memory polynomial or generalized memory polynomial, with fewer parameters. We develop a DPD processor prototype and perform a comparison for different sets of BAPS basis functions to study their effect on both DPD power consumption and performance in terms of PA linearization expressed as Adjacent Channel Power Ratio (ACPR). We present a set of basis functions with 37% lower power consumption and less than 2 dB performance loss compared to BAPS baseline solution.