High-Throughput Low-Power Digital Predistorter Based on Pruned Volterra Series

Paper i proceeding, 2026

Reduced-complexity pruned Volterra series have been shown to deliver good linearization performance for digital predistortion in RF power amplifiers to adequately meet low-power hardware requirements. This paper explores DSP hardware implementation tradeoffs of high-throughput digital predistorters based on pruned Volterra series from which basis functions are selected to jointly optimize linearization performance and DSP power consumption. The proposed HA-BAPS algorithm generates basis functions that lead to a reduction in DSP power consumption. By concurrently processing multiple input samples, hardware parallelism is used to boost throughput. Through hardware reuse, low-power basis functions curb the rise in power consumption while maintaining high linearization performance. Total bitwidth reduction and relaxation of the IEEE-754 floating-point standard further decreases area and power consumption. Four basis sets configurations are explored for floating-point bitwidths of 16, 14, and 12 bits, with both strict and relaxed IEEE-754 standard. We design parallel hardware prototypes that process four input/output samples. The prototype with the best linearization performance vs. power efficiency vs. throughput tradeoff is compared to a baseline prototype with only linearization performance-aware basis functions. A 14-bit floating-point design which abandons IEEE-754 support achieves an improvement in throughput up to 2.2 GS/s. Compared to a parallel baseline design, this consumes 80 mW less power with a performance loss of only 0.32 dB in NMSE.