A VLSI Array Architecture for Artificial Neural Networks

Paper i proceeding, 2003

A highly parallel array architecture for ANN algorithms is presented and evaluated. The array, consisting of PEs inter-connected as a 2D-grid, executes instructions according to the SIMD (Single Instruction Multiple Data) parallel computing model. The architecture is scalable, both in terms of problem size and when porting it to future down-scaled CMOS processes. As typical ANN examples, the feed-forward net with back-propagation training, and the Kohonen Self Organizing Feature Map are used. Performance metrics such as Connection-Updates-Per-Second (CUPS) and Connections-Per-Second (CPS) are derived based on test implementations. A VLSI test chip design is presented in order to show the feasibility of implementing the architecture.