Single stage CMOS Power Amplifier at 23 GHz

Övrigt konferensbidrag, 2007

A single stage CMOS power amplifier (PA) is designed and characterized. According to simulations, a power added efficiency (PAE) of 20% is achieved with 5 dB of gain and 12 dBm of output power at 23GHz. Differences between measurement and simulation are observed. A through analysis explaining these differences is presented. Measurements show a frequency shift to 18.9 GHz with 10dBm of output power, PAE equal to 5%, and a gain of 3.2 dB. The frequency shift is mainly related to the effect of RF-pads which are measured to be as a parallel capacitor with a value of 200 fF. The design was based on device model provided by the foundry which did not include extrinsic parasitic components especially the gate resistance which is the main reason for gain degradation.