PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor
Artikel i vetenskaplig tidskrift, 2016

Hardware prefetching on IBM’s latest POWER8 processor is able to improve performance of many applications significantly, but it can also cause performance loss for others. The IBM POWER8 processor provides one of the most sophisticated hardware prefetching designs which supports 225 different configurations. Obviously, it is a big challenge to find the optimal or near-optimal hardware prefetching configuration for a specific application. We present a dynamic prefetching tuning scheme in this paper, named Prefetch Automatic Tuner (PATer). PATer uses a prediction model based on machine learning to dynamically tune the prefetch configuration based on the values of hardware performance monitoring counters (PMCs). By developing a two-phase prefetching selection algorithm and a prediction accuracy optimization algorithm in this tool, we identify a set of selected key hardware prefetch configurations that matter mostly to performance as well as a set of PMCs that maximize the machine learning prediction accuracy. We show that PATer is able to accelerate the execution of diverse workloads up to 1.4x.


Computer architecture

memory hierarchy


Minghua Li

Guancheng Chen

Qijun Wang

Yong Hua Lin

Per Stenström

Chalmers, Data- och informationsteknik, Datorteknik

Peter Hofstee

IEEE Computer Architecture Letters

1556-6056 (ISSN) 15566064 (eISSN)

Vol. 15 1 37-40 7120125


Informations- och kommunikationsteknik


Data- och informationsvetenskap

Elektroteknik och elektronik



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