AVR: Reducing Memory Traffic with Approximate Value Reconstruction
Paper i proceeding, 2019

This paper describes Approximate Value Reconstruction (AVR), an architecture for approximate memory compression. AVR reduces the memory traffic of applications that tolerate approximations in their dataset. Thereby, it utilizes more efficiently off-chip bandwidth improving significantly system performance and energy efficiency. AVR compresses memory blocks using low latency downsampling that exploits similarities between neighboring values and achieves aggressive compression ratios, up to 16:1 in our implementation. The proposed AVR architecture supports our compression scheme maximizing its effect and minimizing its overheads by (i) co-locating in the Last Level Cache (LLC) compressed and uncompressed data, (ii) efficiently handling LLC evictions, (iii) keeping track of badly compressed memory blocks, and (iv) avoiding LLC pollution with unwanted decompressed data. For applications that tolerate aggressive approximation in large fractions of their data, AVR reduces memory traffic by up to 70%, execution time by up to 55%, and energy costs by up to 20% introducing less than 1% error to the application output.


Approximate Computing

Cache Compression


Albin Eldstål Damlin

Chalmers, Data- och informationsteknik, Datorteknik

Pedro Petersen Moura Trancoso

Chalmers, Data- och informationsteknik, Datorteknik

Ioannis Sourdis

Chalmers, Data- och informationsteknik, Datorteknik

ACM International Conference Proceeding Series

Vol. 5 August 2019 a4
978-145036295-5 (ISBN)

48th International Conference on Parallel Processing, ICPP 2019
Kyoto, Japan,

ACE: Approximativa algoritmer och datorsystem

Vetenskapsrådet (VR) (2014-6221), 2015-01-01 -- 2018-12-31.






Informations- och kommunikationsteknik


C3SE (Chalmers Centre for Computational Science and Engineering)



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