L2C: Combining Lossy and Lossless Compression on Memory and I/O
Artikel i vetenskaplig tidskrift, 2022

In this paper we introduce L2C, a hybrid lossy/lossless compression scheme applicable both to the memory subsystem and I/O traffic of a processor chip. L2C employs general-purpose lossless compression and combines it with state of the art lossy compression to achieve compression ratios up to 16:1 and improve the utilization of chip's bandwidth resources. Compressing memory traffic yields lower memory access time, improving system performance and energy efficiency. Compressing I/O traffic offers several benefits for resource-constrained systems, including more efficient storage and networking.
We evaluate L2C as a memory compressor in simulation with a set of approximation-tolerant applications. L2C improves baseline execution time by an average of 50\%, and total system energy consumption by 16%. Compared to the lossy and lossless current state of the art memory compression approaches, L2C improves execution time by 9% and 26% respectively, and reduces system energy costs by 3% and 5%, respectively.
I/O compression efficacy is evaluated using a set of real-life datasets. L2C achieves compression ratios of up to 10.4:1 for a single dataset and on average about 4:1, while introducing no more than 0.4% error.

Memory Systems

Approximate Computing



Albin Eldstål-Ahrens

Chalmers, Data- och informationsteknik, Datorteknik

Angelos Arelakis

ZeroPoint Technologies

Ioannis Sourdis

Chalmers, Data- och informationsteknik, Datorteknik

Transactions on Embedded Computing Systems

1539-9087 (ISSN) 15583465 (eISSN)

Vol. 21 1 12

ACE: Approximativa algoritmer och datorsystem

Vetenskapsrådet (VR) (2014-6221), 2015-01-01 -- 2018-12-31.


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