Feature-based SpMV Performance Analysis on Contemporary Devices
Paper i proceeding, 2023

The SpMV kernel is characterized by high performance variation per input matrix and computing platform. While GPUs were considered State-of-the-Art for SpMV, with the emergence of advanced multicore CPUs and low-power FPGA accelerators, we need to revisit its performance and energy efficiency. This paper provides a high-level SpMV performance analysis based on structural features of matrices related to common bottlenecks of memory-bandwidth intensity, low ILP, load imbalance and memory latency overheads. Towards this, we create a wide artificial matrix dataset that spans these features and study the performance of different storage formats in nine modern HPC platforms; five CPUs, three GPUs and an FPGA. After validating our proposed methodology using real-world matrices, we analyze our extensive experimental results and draw key insights on the competitiveness of different target architectures for SpMV and the impact of each feature/bottleneck on its performance.

performance analysis

Sparse Matrix-Vector Multiplication

Författare

Panagiotis Mpakos

National Technical University of Athens (NTUA)

Dimitrios Galanopoulos

National Technical University of Athens (NTUA)

Petros Anastasiadis

National Technical University of Athens (NTUA)

Nikela Papadopoulou

Chalmers, Data- och informationsteknik, Datorteknik

Nectarios Koziris

National Technical University of Athens (NTUA)

Georgios Goumas

National Technical University of Athens (NTUA)

Proceedings - 2023 IEEE International Parallel and Distributed Processing Symposium, IPDPS 2023

668-679
9798350337662 (ISBN)

37th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2023
St. Petersburg, USA,

Ämneskategorier

Datavetenskap (datalogi)

DOI

10.1109/IPDPS54959.2023.00072

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2024-01-03