KASYAB PARMESH SUBRAMANIYAN

Showing 14 publications

2014

On DFM Considerations and Assessment for Nanometer SoCs

KASYAB PARMESH SUBRAMANIYAN
Doctoral thesis
2014

MIDAS: Model for IP-inclusive DFM assessment of system manufacturability

KASYAB PARMESH SUBRAMANIYAN, Per Larsson-Edefors
5th European Workshop on CMOS Variability, VARI 2014. Palma de Mallorca, SPAIN, SEP 29-OCT 01, 2014, p. Art. no. 6957079-
Paper in proceedings
2013

Manufacturable Nanometer Designs using Standard Cells with Regular Layout

KASYAB PARMESH SUBRAMANIYAN, Per Larsson-Edefors
Proceedings - International Symposium on Quality Electronic Design, ISQED, p. 398-405
Paper in proceedings
2012

On Regularity and Integrated DFM Metrics

KASYAB PARMESH SUBRAMANIYAN, Per Larsson-Edefors
4th Asia Symposium on Quality Electronic Design (ASQED), Malaysia, July 10-11, 2012, p. 211-218
Paper in proceedings
2011

Application-Specific Energy Optimization of General-Purpose Datapath Interconnect

Babak Hidaji, Salar Alipour, KASYAB PARMESH SUBRAMANIYAN et al
Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), p. 301-306
Paper in proceedings
2011

FlexDEF: Development Framework for Processor Architecture Implementation and Evaluation

KASYAB PARMESH SUBRAMANIYAN, Erik J Ryman, Magnus Själander et al
Proceedings of 7th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), p. 37-40
Paper in proceedings
2010

Datapath Interconnect Optimization Engine for Energy-Efficient FlexCore Configurations

Babak Hidaji, Salar Alipour, Jacob Lidman et al
Swedish System-on-Chip Conference
Conference contribution
2010

Design Space Exploration for an Embedded Processor with Flexible Datapath Interconnect

Tung Hoang, Ulf Jälmbrant, Erik der Hagopian et al
Proceedings of IEEE Int. Conf. on Application-specific Systems, Architectures and Processors (ASAP), p. 55-62
Paper in proceedings
2010

FlexTools: Design Space Exploration Tool Chain from C to Physical Implementation

Erik J Ryman, KASYAB PARMESH SUBRAMANIYAN, Tung Hoang et al
CDNLive! EMEA
Paper in proceedings
2010

Impact of Standard Cell Pin Placement on Routing Regularity of HPM Architectures

Affaq Qamar, KASYAB PARMESH SUBRAMANIYAN, Per Larsson-Edefors
Swedish System-on-Chip Conference
Conference contribution
2010

Generation and Exploration of Layouts for Area-Efficient Barrel Shifters

Alen Bardizbanyan, KASYAB PARMESH SUBRAMANIYAN, Per Larsson-Edefors
Proceedings of IEEE Computer Society Annual Symp. on VLSI (ISVLSI), p. 454-455
Paper in proceedings
2009

Fast Layout Exploration Using the Wired System

Emil Axelsson, KASYAB PARMESH SUBRAMANIYAN, Mary Sheeran et al
Swedish System-on-Chip Conference (SSoCC)
Conference contribution
2009

Layout Exploration of Geometrically Accurate Arithmetic Circuits

KASYAB PARMESH SUBRAMANIYAN, Emil Axelsson, Mary Sheeran et al
Proceedings of IEEE International Conference of Electronics, Circuits and Systems
Paper in proceedings
2009

Custom Layout Strategy for Rectangle-Shaped Log-Depth Multiplier Reduction Tree

Patrik Kimfors, Niklas Broman, Andreas Haraldsson et al
Proceedings of IEEE International Conference of Electronics, Circuits and Systems
Paper in proceedings

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