Showing 13 publications
Custom Layout Strategy for Rectangle-Shaped Log-Depth Multiplier Reduction Tree
Toward Architecture-Based Test-Vector Generation for Timing Verification of Fast Parallel Multipliers
Multiplier Reduction Tree with Logarithmic Logic Depth and Regular Connectivity
A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating
A Power Cut-Off Technique for Gate Leakage Suppression
An Efficient Twin-Precision Multiplier
Glitch-Conscious Low-Power Design of Arithmetic Circuits
Dynamic Pass-Transistor Dot Operators for Efficient Parallel-Prefix Adders
Efficient Implementation and Analysis of CMOS Arithmetic Circuits
Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects
Characterizing Ripple-Carry Circuits Using Logical Effort
Full-Custom vs. Standard-Cell Design Flow - An Adder Case Study
Full-Custom vs. Standard-Cell Based Design – An Adder Comparison
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