The concept of this project is to unlock the potential of epitaxial graphene on silicon carbide (SiC) for development of scalable electronics with the view to develop graphene-based devices & circuits with a non-conventional functionality. Our strategy is to explore two promising directions of graphene-based technology: (i) the development of large-scale graphene wafers for manufacturing high-density of devices on a single SiC wafer, and (ii) the development of hybrid circuits for applications of graphene in spintronics and metrology by exploiting the flexibility for design offered by the large area of graphene on SiC. The consortium of bidders brings together groups with complementary expertise and substantial achievements in the relevant area of graphene research and nanotechnology in general.
The objectives are to (1) reliably produce large-area graphene with a controlled carrier density and improved transport characteristics; (2) pattern graphene for applications using industrial nanostructuring and nanofabrication methods, aiming at high integration densities with a good yield of working devices; (3) produce a prototype for a graphene-based Quantum Hall Resistance standard with characteristics surpassing existing silicon- and GaAs-based devices; (4) develop a pilot version of spintronic devices of epitaxial graphene; (5) start exploiting the commercial potential of graphene by establishing a start-up company that will produce graphene wafers for users outside this consortium.
These objectives relate directly to major parts of the call, namely, the need for new circuit architechtures, metrology and characterization techniques; new device structures for non-Si and Si based advanced integrated components to add functionality to circuits and (sub)systems; and new technologies and functional devices beyond CMOS.
Professor at Chalmers, Microtechnology and Nanoscience (MC2), Applied Quantum Physics
Lancaster, United Kingdom
Hook, United Kingdom
Funding Chalmers participation during 2010–2013