Boron impurity at the Si/SiO2 interface in SOI wafers and consequences for piezoresistive MEMS devices
Journal article, 2009

In this work, the electrical performance of piezoresistive devices fabricated on thinned SOI wafers has been investigated. Specifically, SOI wafers manufactured with the standard bond-and-etch back method (BESOI), commonly used for MEMS fabrication, have been studied. Results from electrical measurements and SIMS characterization show the presence of a boron impurity close to the buried oxide, even on unprocessed wafers. If the boron impurity overlaps with the piezoresistors on the device, it can create non-defined pn-junctions and thus allow conduction through the substrate, leading to stray connections and excessive noise. The thickness of the boron impurity can extend up to several μm, thus setting a thickness limit for the thinnest parts of a MEMS device. This work shows how this impurity can fundamentally affect the functionality of piezoresistive devices. Design rules of how to avoid this are presented

Boron impurity

Piezoresistive

MEMS

SOI

Author

Alexandra Nafari

Chalmers, Applied Physics, Electronics Material and Systems Laboratory

Cristina Rusu

Imego AB - The Institute of Micro and Nanotechnology

Krister Svensson

Karlstad University

Peter Enoksson

Chalmers, Applied Physics, Electronics Material and Systems Laboratory

Journal of Micromechanics and Microengineering

0960-1317 (ISSN)

Vol. 19 1 6-

Areas of Advance

Nanoscience and Nanotechnology (2010-2017)

Materials Science

Infrastructure

Nanofabrication Laboratory

Subject Categories

Other Electrical Engineering, Electronic Engineering, Information Engineering

DOI

10.1088/0960-1317/19/1/015034

More information

Latest update

5/23/2018