Hysteresis modeling in graphene field effect transistors
Journal article, 2015

Graphene field effect transistors with an Al2O3 gate dielectric are fabricated on H-intercalated bilayer graphene grown on semi-insulating 4H-SiC by chemical vapour deposition. DC measurements of the gate voltage nu(g) versus the drain current i(d) reveal a severe hysteresis of clockwise orientation. A capacitive model is used to derive the relationship between the applied gate voltage and the Fermi energy. The electron transport equations are then used to calculate the drain current for a given applied gate voltage. The hysteresis in measured data is then modeled via a modified Preisach kernel.

Author

Michael Winters

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics

Einar Sveinbjörnsson

University of Iceland

Niklas Rorsman

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics

Journal of Applied Physics

0021-8979 (ISSN) 1089-7550 (eISSN)

Vol. 117 7 Art. no, 074501- 074501

Graphene-Based Revolutions in ICT And Beyond (Graphene Flagship)

European Commission (FP7), 2013-10-01 -- 2016-03-31.

Subject Categories

Other Engineering and Technologies

Nano Technology

DOI

10.1063/1.4913209

More information

Latest update

11/23/2018