Hysteresis modeling in graphene field effect transistors
Artikel i vetenskaplig tidskrift, 2015

Graphene field effect transistors with an Al2O3 gate dielectric are fabricated on H-intercalated bilayer graphene grown on semi-insulating 4H-SiC by chemical vapour deposition. DC measurements of the gate voltage nu(g) versus the drain current i(d) reveal a severe hysteresis of clockwise orientation. A capacitive model is used to derive the relationship between the applied gate voltage and the Fermi energy. The electron transport equations are then used to calculate the drain current for a given applied gate voltage. The hysteresis in measured data is then modeled via a modified Preisach kernel.


Michael Winters

Chalmers, Mikroteknologi och nanovetenskap (MC2), Mikrovågselektronik

Einar Sveinbjörnsson

Háskóli Íslands

Niklas Rorsman

Chalmers University of Technology

Journal of Applied Physics

0021-8979 (ISSN) 1089-7550 (eISSN)

Vol. 117 Art. no, 074501- 074501


Annan teknik