Industrial Temporal Logic Specifications for Falsification of Cyber-Physical Systems
Paper in proceeding, 2020
In this benchmark proposal, we present a set of large specifications stated in Signal Temporal Logic (STL) intended for use in falsification of Cyber-Physical Systems. The main purpose of the benchmark is for tools that monitor STL specifications to be able to test their performance on complex specifications that have structure similar to industrial specifications. The benchmark itself is a Git repository which will therefore be updated over time, and new specifications can be added. At the time of submission, the repository contains a total of seven Simulink requirement models, resulting in 17 generated STL specifications.
Benchmark
Temporal Logic
Cyber-Physical Systems
Falsification
Author
Johan Lidén Eddeland
Chalmers, Electrical Engineering, Systems and control
Alexandre Donzé
Decyphir SAS
Sajed Miremadi
Chalmers, Electrical Engineering, Systems and control
Knut Åkesson
Chalmers, Electrical Engineering, Systems and control
EPiC Series in Computing
23987340 (eISSN)
Vol. 74 267-274
7th International Workshop on Applied Verification for Continuous and Hybrid Systems
Berlin (onliine), Germany,
Berlin (onliine), Germany,
Model Based Testing of Mechatronic Systems (TESTRON)
VINNOVA (2015-04893), 2016-01-01 -- 2019-12-31.
Systematic testing of cyber-physical systems (SyTeC)
Swedish Research Council (VR) (2016-06204), 2017-01-01 -- 2022-12-31.
Subject Categories
Computer Engineering
Embedded Systems
Computer Science
DOI
10.29007/r74f