Gate-recess Technology for InAs/AlSb HEMTs
Journal article, 2009

The gate-recess technology for Si δ-doped InAs/AlSb high-electron-mobility transistors (HEMTs) has been investigated by combining atomic force microscopy (AFM) inspection of the gate-recess versus time with electrical device characterization. Deposition of the gate metal on the In0.5Al0.5As protection layer or on the underlying AlSb Schottky layer resulted in devices suffering from high gate-leakage current. Superior dc and high frequency device performance were obtained for HEMTs with an insulating layer between the gate and the Schottky layer resulting in a reduction of the gate leakage current IG by more than two orders of magnitude at a drain-to-source voltage VDS of 0.1 V. The existence of this intermediate insulating layer was evident from the electrical measurements. AFM measurements suggested that the insulating layer was due to a native oxidation of the AlSb Schottky layer. The insulated-gate HEMT with a gate length of 225 nm exhibited a maximum drain current ID higher than 500 mA/mm with good pinchoff characteristics, a dc transconductance gm of 1300 mS/mm, and extrinsic values for cutoff frequency fT and maximum frequency of oscillation fmax of 160 and 120 GHz, respectively.



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Eric Lefebvre

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics

Mikael Malmkvist

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics

Malin Borg

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics

Ludovic Desplanque

University of Lille

Xavier Wallart

University of Lille

Gilles Dambrine

University of Lille

Sylvain Bollaert

University of Lille

Jan Grahn

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics

IEEE Transactions on Electron Devices

0018-9383 (ISSN) 15579646 (eISSN)

Vol. 56 9 1904-1911

Subject Categories

Other Electrical Engineering, Electronic Engineering, Information Engineering



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