A Mixed-Mode Delay-Locked Loop Architecture
Paper in proceedings, 2003

We present a mixed-mode delay-locked loop (DLL) architecture intended for multiple-phase clock generation. In contrast to analog DLLs, the proposed architecture allows for clock-gating; moreover circuit simulations indicate that its performance (in terms of maximum frequency, frequency range, and low-speed power dissipation) is superior to that of a previously-reported, purely digital DLL.

Author

Daniel Eckerbert

Chalmers, Department of Computer Engineering, Integrated Electronic Systems

Lars Svensson

Chalmers, Department of Computer Engineering, Integrated Electronic Systems

Per Larsson-Edefors

Chalmers, Department of Computer Engineering, Integrated Electronic Systems

Proceedings of the 21st International Conference on Computer Design (ICCD), San Jose, 13-15 October 2003

1063-6404 (ISSN)

261-263

Subject Categories

Other Electrical Engineering, Electronic Engineering, Information Engineering

DOI

10.1109/ICCD.2003.1240904

ISBN

0-7695-2025-1

More information

Created

10/7/2017