Dynamic Equalizer Power Dissipation Optimization
Paper in proceeding, 2016
We investigate power dissipation/performance trade-off in a 28nm ASIC implementation of a parallel dynamic equalizer. Over 50% dissipation improvement is possible by sample pruning during filter updates, with only minor tracking-performance reduction.
Author
Christoffer Fougstedt
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Pontus Johannisson
Chalmers, Microtechnology and Nanoscience (MC2), Photonics
Lars Svensson
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Per Larsson-Edefors
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
2016 Optical Fiber Communications Conference and Exhibition
978-1-9435-8007-1 (ISBN)
Areas of Advance
Information and Communication Technology
Driving Forces
Sustainable development
Subject Categories
Other Electrical Engineering, Electronic Engineering, Information Engineering
ISBN
978-1-9435-8007-1