Process optimization for SiGe pMOSFETs using low temperature oxides on ultra-thin cap layers
Paper i proceeding, 2004

We optimized the oxidation and annealing processes for SiGe quantum-well (QW) p-channel Metal-Oxide-Semiconductor Field-Effect Transistors (pMOSFETs) to maintain the strain in the channel and to suppress or eliminate the Si cap layer parasitic conduction. We fabricated and investigated poly-Si gated MOS capacitors incorporating 2nm low-temperature furnace oxides and optimized ultra-thin Si-cap layers. For these structures, we found that a rapid thermal annealing (RTA) thermal budget of 950°C, 30s could serve as a proper choice for gate dopants activation. © Physica Scripta 2004.

Författare

Mikael Johansson

Chalmers

M. Y. A. Yousif

Chalmers, Mikroteknologi och nanovetenskap (MC2), Fasta tillståndets elektronik

Per Lundgren

Chalmers, Mikroteknologi och nanovetenskap (MC2)

Stefan Bengtsson

Chalmers, Mikroteknologi och nanovetenskap (MC2)

Physica scripta. Topical Issues

0281-1847 (ISSN)

Vol. T114 97-99

Ämneskategorier

Materialteknik

Elektroteknik och elektronik

DOI

10.1088/0031-8949/2004/T114/024

Mer information

Senast uppdaterat

2018-09-10