Process optimization for SiGe pMOSFETs using low temperature oxides on ultra-thin cap layers

Paper i proceeding, 2004

We optimized the oxidation and annealing processes for SiGe quantum-well (QW) p-channel Metal-Oxide-Semiconductor Field-Effect Transistors (pMOSFETs) to maintain the strain in the channel and to suppress or eliminate the Si cap layer parasitic conduction. We fabricated and investigated poly-Si gated MOS capacitors incorporating 2nm low-temperature furnace oxides and optimized ultra-thin Si-cap layers. For these structures, we found that a rapid thermal annealing (RTA) thermal budget of 950°C, 30s could serve as a proper choice for gate dopants activation. © Physica Scripta 2004.