On the Modeling of High Power FET Transistors
Paper i proceeding, 2016
The paper address some of the problems faced when modeling high power and high power density GaN and GaAs FETs. When operating a high power levels (>1kW) additional effects are observed in GaN devices that are not seen in low power operation (1W). Similar effects start to act on GaAs devices when operated at high power densities. In order to account for these effects, FET models were extended to include temperature, and bias dependence of the access resistances, as well as inflection points in the transconductance, and capacitances. Thus enabling accurate models of the latest generation of enhancement mode, KV range FETs. The recent extensions are evaluated, implemented, and available in major CAD tools like ADS, Cadence, and Microwave office.
High Power FET