A Surface Potential Model for Predicting Substrate Noise Coupling in Integrated Circuits
Paper i proceeding, 2004

In integrated circuits, it must be verified that noise injected and transmitted through the substrate does not degrade the performance of sensitive circuitry present on the chip. In this paper, we present a simple analytic substrate model for evaluating substrate noise coupling. The model handles an arbitrary number of aggressor and victim devices as well as biased and floating chip backside. The model has been validated by measurements on test structures manufactured in a 0.35 /spl mu/m CMOS process, and it is shown that the model gives an accurate description of the substrate noise coupling. For example, the noise suppressing properties of guard rings have been evaluated.

interference suppression

0.35 micron

integrated circuit modelling

surface potential

integrated circuit noise

CMOS

substrate injected noise

substrate transmitted noise

surface potential model

aggressor devices

guard rings noise suppressing properties

victim devices

biased chip backside

CMOS integrated circuits

IC substrate noise coupling

coupled circuits

floating chip backside

Författare

Simon Kristiansson

Chalmers, Mikroteknologi och nanovetenskap (MC2), Fasta tillståndets elektronik

Fredrik Ingvarson

Chalmers, Mikroteknologi och nanovetenskap (MC2), Fasta tillståndets elektronik

Shiva P. Kagganti

Chalmers, Mikroteknologi och nanovetenskap (MC2), Fasta tillståndets elektronik

Kjell Jeppson

Chalmers, Mikroteknologi och nanovetenskap (MC2), Fasta tillståndets elektronik

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC; Orlando, FL; United States; 3 October 2004 through 6 October 2004

0886-5930 (ISSN)

497-500

Ämneskategorier

Elektroteknik och elektronik

Mer information

Skapat

2017-10-06