research and development of SiC Static Induction transistor
Konferensbidrag (offentliggjort, men ej förlagsutgivet), 2003
A fabrication process for SiC Static Induction Transistors (SITs) is developed and tested. Simulated and measured results of the device are presented. The complete fabrication process involves only 5 lithography steps, due to the self-aligned process used for mesa, ohmic contacts and gates. This makes the process fast and minimize the risk of process errors. Only optical lithography is used in the process, why dimensions are not optimised. Mesa widths of 2, 3, 4 and 5 µm are processed. Since the process is scalable, better performance can be expected with smaller widths achieved by the use electron beam lithography. Preliminary results indicate FET operation with a maximum current density of 110 mA/mm.