Analysis of DC Bus Bar Inductance on Performance of 2-level Inverter

Paper i proceeding, 2024

In a 2-level inverter, the DC bus bar links the power module to the DC-link capacitors. During hard switching of the power semiconductor, the stray inductance of the bus bar generates voltage overshoots across the switch and the DC bus. Existing literature primarily investigates the impact of these overshoots on the inverter's electromagnetic emissions. This paper focuses on assessing the effect of voltage overshoots on inverter switching losses through a combination of Double Pulse Test (DPT) simulations, drive cycle simulations, and experimental voltage overshoot analysis. Two bus bar prototypes with a 26% difference in stray inductance were developed for a 2-level inverter. The switching losses of the semiconductor were evaluated over drive cycles, revealing a 0.94% increase in energy losses due to the higher bus bar inductance. In line with that, switch-level DPT results indicated an increase of 1.14%. This suggests that analyzing inverter switching losses through drive cycle simulations is important as voltage spike measurement which shows a considerable amount of switching energy loss. Further, the voltage overshoot analysis reveals a 12% reduction in voltage stress on the switch attributable to stray inductance both in simulation and experiment.