Autoregressive Stochastic Clock Jitter Compensation in Analog-to-Digital Converters

Artikel i vetenskaplig tidskrift, 2026

This paper addresses the mathematical modeling and compensation of stochastic discrete-time clock jitter in analog-to-digital converters (ADCs). We model the stochastic clock jitter as a first-order autoregressive (AR(1)) process, and we propose two novel, computationally efficient, pilot-assisted dejittering algorithms for baseband signals: one based on solving a sequence of weighted least-squares problems, and another that exploits the correlated jitter structure via a Kalman filterbased routine.We also propose a conditional maximum-likelihood estimator for the autoregressive parameters, enabling nearoptimal Kalman-filter performance even when such parameters vary over time. We further provide a mathematical analysis of the induced linearization errors, and we complement the theory with synthetic simulations to evaluate the proposed techniques across different scenarios. The proposed techniques are shown to yield a 1 – 15 dB improvement in signal-to-noise-and-distortion ratio (SINADR) and 0.02 – 1.6 dB in symbol error vector magnitude (EVM), depending on impairment severity and pilot density. The Kalman smoother generally provides superior performance by leveraging additional temporal information.