A Power Cut-Off Technique for Gate Leakage Suppression
Paper in proceedings, 2004

Gate leakage power dissipation is predicted to overtake subthreshold leakage power within the next few years thus adding further problems for designers trying to meet a strict power budget. In this paper a power cut-off technique is proposed, which in steep mode suppresses not only subthreshold leakage but also gate leakage. The proposed technique displays a combination of low total leakage power and short wake-up time.

Author

Mindaugas Drazdziulis

Chalmers, Department of Computer Engineering, Integrated Electronic Systems

Per Larsson-Edefors

Chalmers, Department of Computer Engineering, Integrated Electronic Systems

Daniel Eckerbert

Chalmers, Department of Computer Engineering, Integrated Electronic Systems

Henrik Eriksson

Chalmers, Department of Computer Engineering, Integrated Electronic Systems

European Solid-State Circuits Conference (ESSCIRC)

171-174

Subject Categories

Computer and Information Science

DOI

10.1109/ESSCIR.2004.1356645

More information

Created

10/7/2017