ASIC Design Exploration for DSP and FEC of 400-Gbitis Coherent Data-Center Interconnect Receivers
Paper in proceeding, 2020

We perform exploratory ASIC design of key DSP and FEC units for 400-Gbit/s coherent data-center interconnect receivers. In 22-nm CMOS, the considered units together dissipate 5 W, suggesting implementation feasibility in power-constrained form factors.

Author

Christoffer Fougstedt

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers), Electronics Systems

Oscar Gustafsson

Linköping University

Cheolyong Bae

Linköping University

Erik Börjeson

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers), Electronics Systems

Per Larsson-Edefors

Electric, Computer, IT and Industrial Engineering

2020 OPTICAL FIBER COMMUNICATIONS CONFERENCE AND EXPOSITION (OFC)

Optical Fiber Communications Conference and Exposition (OFC)
San Diego, CA, USA,

Subject Categories

Architectural Engineering

Computer Engineering

Other Electrical Engineering, Electronic Engineering, Information Engineering

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Latest update

9/10/2021