Using Valued Booleans to Find Simpler Counterexamples in Random Testing of Cyber-Physical Systems
Paper i proceeding, 2018

We propose a new logic of valued Booleans for writing properties which are not just true or false but compute how severely they are falsified. The logic is reminiscent of STL or MTL but gives the tester control over what severity means in the particular problem domain. We use this logic to simplify failing test inputs in the context of random testing of cyber-physical systems and show that it improves the quality of counterexamples found. The logic of valued Booleans might also be used as an alternative to the standard robust semantics of STL formulas in optimization-based approaches to falsification.

model-driven systems engineering

logical design, physical design and implementation of embedded computer systems

Reachability analysis, verification and abstraction of hybrid systems

embedded computer control systems and applications

supervision and testing

Författare

Koen Lindström Claessen

Chalmers, Data- och informationsteknik, Funktionell programmering

Nicholas Smallbone

Chalmers, Data- och informationsteknik, Funktionell programmering

Johan Lidén Eddeland

Volvo Cars

Chalmers, Elektroteknik, System- och reglerteknik, Automation

Zahra Ramezani

Chalmers, Elektroteknik, System- och reglerteknik, Automation

Knut Åkesson

Chalmers, Elektroteknik, System- och reglerteknik, Automation

IFAC-PapersOnLine

2405-8963 (ISSN)

Vol. 51 7 408-415

14th IFAC International Workshop on Discrete Event Systems (WODES)
, Italy,

Modellbaserad Testning av Mekatroniska System (TESTRON)

VINNOVA, 2016-01-01 -- 2019-12-31.

Systematisk testning av cyberfysiska system (SyTeC)

Vetenskapsrådet (VR), 2017-01-01 -- 2022-12-31.

Ämneskategorier

Reglerteknik

Datavetenskap (datalogi)

Datorsystem

DOI

10.1016/j.ifacol.2018.06.333

Mer information

Senast uppdaterat

2018-09-12