Using Valued Booleans to Find Simpler Counterexamples in Random Testing of Cyber-Physical Systems
Paper i proceeding, 2018
We propose a new logic of valued Booleans for writing properties which are not just true or false but compute how severely they are falsified. The logic is reminiscent of STL or MTL but gives the tester control over what severity means in the particular problem domain. We use this logic to simplify failing test inputs in the context of random testing of cyber-physical systems and show that it improves the quality of counterexamples found. The logic of valued Booleans might also be used as an alternative to the standard robust semantics of STL formulas in optimization-based approaches to falsification.
Reachability analysis, verification and abstraction of hybrid systems
logical design, physical design and implementation of embedded computer systems
supervision and testing
embedded computer control systems and applications
model-driven systems engineering
Författare
Koen Lindström Claessen
Chalmers, Data- och informationsteknik, Funktionell programmering
Nicholas Smallbone
Chalmers, Data- och informationsteknik, Funktionell programmering
Johan Lidén Eddeland
Volvo Cars
Chalmers, Elektroteknik, System- och reglerteknik
Zahra Ramezani
Chalmers, Elektroteknik, System- och reglerteknik
Knut Åkesson
Chalmers, Elektroteknik, System- och reglerteknik
IFAC-PapersOnLine
24058971 (ISSN) 24058963 (eISSN)
Vol. 51 7 408-415
14th IFAC International Workshop on Discrete Event Systems (WODES)
, Italy,
, Italy,
Modellbaserad Testning av Mekatroniska System (TESTRON)
VINNOVA (2015-04893), 2016-01-01 -- 2019-12-31.
Systematisk testning av cyberfysiska system (SyTeC)
Vetenskapsrådet (VR) (2016-06204), 2017-01-01 -- 2022-12-31.
Ämneskategorier
Reglerteknik
Datavetenskap (datalogi)
Datorsystem
DOI
10.1016/j.ifacol.2018.06.333