DDRNoC: Dual Data-Rate Network-on-Chip
Artikel i vetenskaplig tidskrift, 2018

This article introduces DDRNoC, an on-chip interconnection network capable of routing packets at Dual Data Rate. The cycle time of current 2D-mesh Network-on-Chip routers is limited by their control as opposed to the datapath (switch and link traversal), which exhibits significant slack. DDRNoC capitalizes on this observation, allowing two flits per cycle to share the same datapath. Thereby, DDRNoC achieves higher throughput than a Single Data Rate (SDR) network. Alternatively, using lower voltage circuits, the above slack can be exploited to reduce power consumption while matching the SDR network throughput. In addition, DDRNoC exhibits reduced clock distribution power, improving energy efficiency, as it needs a slower clock than a SDR network that routes packets at the same rate. Post place and route results in 28nm technology show that, compared to an iso-voltage (1.1V) SDR network, DDRNoC improves throughput proportionally to the SDR datapath slack. Moreover, a low-voltage (0.95V) DDRNoC implementation converts that slack to power reduction offering the 1.1V SDR throughput at a substantially lower energy cost.

On-chip-interconnect

Författare

Ahsen Ejaz

Chalmers, Data- och informationsteknik, Datorteknik

Vasileios Papaefstathiou

Chalmers, Data- och informationsteknik, Datorteknik

Ioannis Sourdis

Chalmers, Data- och informationsteknik, Datorteknik

Transactions on Architecture and Code Optimization

1544-3566 (ISSN) 1544-3973 (eISSN)

Vol. 15 2 25

Energy-efficient Heterogeneous COmputing at exaSCALE (ECOSCALE)

Europeiska kommissionen (Horisont 2020), 2015-10-01 -- 2018-12-31.

Ämneskategorier

Telekommunikation

Kommunikationssystem

Annan elektroteknik och elektronik

DOI

10.1145/3200201

Mer information

Senast uppdaterat

2018-09-14