Industrial Temporal Logic Specifications for Falsification of Cyber-Physical Systems
Paper i proceeding, 2020

In this benchmark proposal, we present a set of large specifications stated in Signal Temporal Logic (STL) intended for use in falsification of Cyber-Physical Systems. The main purpose of the benchmark is for tools that monitor STL specifications to be able to test their performance on complex specifications that have structure similar to industrial specifications. The benchmark itself is a Git repository which will therefore be updated over time, and new specifications can be added. At the time of submission, the repository contains a total of seven Simulink requirement models, resulting in 17 generated STL specifications.

Falsification

Cyber-Physical Systems

Benchmark

Temporal Logic

Författare

Johan Lidén Eddeland

Chalmers, Elektroteknik, System- och reglerteknik, Automation

Alexandre Donzé

Decyphir SAS

Sajed Miremadi

Chalmers, Elektroteknik, System- och reglerteknik, Automation

Knut Åkesson

Chalmers, Elektroteknik, System- och reglerteknik, Automation

7th International Workshop on Applied Verification for Continuous and Hybrid Systems

7th International Workshop on Applied Verification for Continuous and Hybrid Systems
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Modellbaserad Testning av Mekatroniska System (TESTRON)

VINNOVA, 2016-01-01 -- 2019-12-31.

Systematisk testning av cyberfysiska system (SyTeC)

Vetenskapsrådet (VR), 2017-01-01 -- 2022-12-31.

Ämneskategorier

Datorteknik

Inbäddad systemteknik

Datavetenskap (datalogi)

Mer information

Senast uppdaterat

2020-09-11