A Low-Power Cryogenic Low-Noise Amplifier for the Next-Generation Quantum Computers

Journal article, 2026

Next generation of quantum computers calls for reduced dc power dissipation of the cryogenic low-noise amplifier (LNA) applied in reading out the superconducting qubits. This article reports on processing and evaluation of a 100-nm gate length indium phosphide high electron mobility transistor (InP HEMT) technology used in the design of such LNAs. InP HEMTs with size of 4 & times; 50 & micro;m were measured on-wafer by DC and S-parameter characterization. Device noise performance was indirectly evaluated by measuring and modeling the gain and noise of a three-stage hybrid 4-8 GHz cryogenic LNA equipped with the InP HEMTs. When operating the LNA at a DC power of 2.1 mW, the InP HEMT LNA average noise temperature was 1.4 K with an average gain of 41.6 dB. The minimum noise temperature of the InP HEMT was estimated to be 1.1 K at 6 GHz. The performance achieved for the InP HEMT LNA is comparable to the LNAs currently used in quantum computing while requiring only 27% of the DC power consumption. Small-signal modeling of the InP HEMT suggested that this was due to a low output conductance associated with a large gate-recess length used in device fabrication.