Mindaugas Drazdziulis

Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays

Capturing Process-Voltage-Temperature (PVT) Variations in Architectural Static Power Modeling for SRAM Arrays

High-Accuracy Architecture-Level Power Estimation for Partitioned Arrays in a 65-nm CMOS BPTM Process

Overdrive Power-Gating Techniques for Total Power Minimization

Current Probing Methodology for Static Power Extraction in Sub-90nm CMOS Circuits

Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration

Static Power Reduction and Estimation in CMOS Circuits Considering Emerging Leakage Mechanisms

Architecture-Level Power Estimation and Scaling Trends for SRAM Arrays

A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating

Evaluation of Power Cut-Off Techniques in the Presence of Gate Leakage

A Power Cut-Off Technique for Gate Leakage Suppression

Sleep-Mode Circuit Techniques in the Presence of Gate Leakage

A Comparison of Power Cut-Off Techniques Employed for Ripple Carry Adders in the Presence of Gate Leakage

An Investigation of Gate Leakage for Future CMOS Circuits

A Gate Leakage Reduction Strategy for Future CMOS Circuits