Characterization of Drain-Induced Barrier Lowering in GaN HEMTs Using a Drain Current Injection Technique

Journal article, 2024

Assessing short channel effects (SCEs) is crucial in the high-frequency optimization of downscaled field-effect transistors (FETs) such as GaN high electron mobility transistors (HEMTs). Drain-induced barrier lowering (DIBL) is commonly used for quantifying the ability of the gate to modulate the drain-source current at high drain voltages. DIBL is traditionally extracted from the relative shift of the threshold voltage at different drain-source voltages. In this article, we propose a new method based on a drain current injection technique (DCIT) to assess DIBL. This method facilitates a direct measure of the threshold voltage over a wide range of drain-source voltages in a single measurement. The method is demonstrated and compared to the conventional method using AlGaN/GaN and InAlGaN HEMTs with a Fe-doped buffer and a C-doped AlGaN back-barrier, respectively. Furthermore, the impact of different gate lengths and GaN channel layer thicknesses is presented. The measurements are analyzed and discussed with supporting technology computer-aided design (TCAD) simulations. The proposed method facilitates a more general and detailed measurement of the DIBL for HEMTs.