Per Stenström
Showing 193 publications
SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations
eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem
SCALE: Secure and Scalable Cache Partitioning
GBDI: Going Beyond Base-Delta-Immediate Compression with Global Bases
Bounding the execution time of parallel applications on unrelated multiprocessors
CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling
Federated Scheduling of Sporadic DAGs on Unrelated Multiprocessors
DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors
A GPU Register File using Static Data Compression
QoS-driven coordinated management of resources to save energy in multi-core systems
Trends on heterogeneous and innovative hardware and software systems
SimICS/sun4m: A virtual workstation
SaC: Exploiting execution-time slack to save energy in heterogeneous multicore systems
Global dead-block management for task-parallel programs
ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness
Scheduling parallel real-time recurrent tasks on multicore platforms
Runtime-Assisted Global Cache Management for Task-based Parallel Programs
Rock: A framework for pruning the design space of hybrid main memory systems
SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures
Timing-anomaly free dynamic scheduling of task-based parallel applications
RADAR: Runtime-assisted dead region management for last-level caches
PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor
Adaptive row addressing for cost-efficient parallel memory protocols in large-capacity memories
Timing-anomaly free dynamic scheduling of task-based parallel applications
RADAR: Run-time assisted Dead-Region Management for Last-Level Caches
ProF: Probabilistic Hybrid Main Memory Management for High Performance and Fairness
EUROSERVER: Share-anything scale-out micro-server design
A Case for Runtime-Assisted Global Cache Management
A Primer on Compression in the Memory Hierarchy
Enhancing Garbage Collection Synchronization using Explicit Bit Barriers
RADAR: Runtime-Assisted Dead Region Management for Last-Level Caches
Performance Impact of Batching Web Application Requests using Hot-spot Processing on GPUs
HyComp: A Hybrid Cache Compression Method for Selection of Data-Type-Specific Compression Methods
ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory
Introduction to the JPDC special issue on Perspectives on Parallel and Distributed Processing
Characterizing and Exploiting Small-Value Memory Instructions
A Design-Time Resource Partitioning Method for Hybrid Main Memory
A Case for a Value-Aware Cache
Temporal Partitioning on Multicore Platform
Performance and energy analysis of the restricted transactional memory implementation on haswell
Crystal: A design-time resource partitioning method for hybrid main memory
Proceedings of the 2014 ACM International Conference on Supercomputing
Removal of Conflicts in Hardware Transactional Memory Systems
Overhead-Aware Temporal Partitioning on Multicore Processors
Effective Resource Management Towards Efficient Computing
SC2: A statistical compression cache scheme
Runtime-guided cache coherence optimizations in multi-core architectures
Efficient Forwarding of Producer-Consumer Data in Task-based Programs
Towards automatic resource management in parallel architectures.
Improving Data Access Efficiency by Using a Tagless Access Buffer (TAB)
Runtime-Guided Cache Coherence Optimizations in Multi-core Architectures
Moving from Petaflops to Petadata
Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory
HARP: Adaptive Abort Recurrence Prediction for Hardware Transactional Memory
Efficient Forwarding of Producer-Consumer Data in Task-based Programs
Transactional Prefetching: Narrowing the Window of Contention in Hardware Transactional Memory
Transactions on Architectures and Code Optimizations
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory
Transactional prefetching: Narrowing the window of contention in hardware transactional memory
A Data Forwarding Scheme for Task-based Programming Models
Transactional Prefetching: Narrowing the Window of Contention in Hardware Transaction Memory
Critical lock analysis: Diagnosing critical section bottlenecks in multithreaded applications
Transactions on High Performance and Embedded Architectures and Compilers - Vol 4
Techniques for Reduction of Conflicts in Hardware Transactional Memory.
Transactions on High-Performance Embedded Architectures and Compilers Vol 3
ZEBRA: A data-centric, hybrid-policy hardware transactional memory design
Transaction on Architectures and Code Optimization
Coherence-Less Model for Shared-Memory, Speculative Multi-core Processors
Implications of Merging Phases on Scalability of Multi-core Architectures
Implications of Merging Phases on Scalability of Multicore Architectures
The impact of non-coherent buffers on lazy hardware transactional memory systems
Hints Based Speculative Execution for Exploiting Probabilistic Parallel Execution.
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory
A Unified Approach to Eliminate Memory Accesses Early
Diagnosing Critical Section Bottlenecks in Multithreaded Applications
Eager meets lazy: The impact of write-buffering on hardware transactional memory
Classification and Elimination of Conflicts in Hardware-Transactional Memory Systems
The Impact of Non-coherent on Lazy HardwareTransactional Memory Systems
Semantic Information Driven Speculative Execution
Characterization and Exploitation of Narrow-Width Loads:The Narrow-Width Cache Approach
LV*: A Class of Lazy-Versioning HTMs for Low-Cost Integration of Transactional Memory Systems
LV*: A Low Complexity Lazy Versioning HTM Infrastructure
Diagnosing Serialization Bottlenecks in Multi-threaded Applications on Multi-core Processors
Characterization and Exploitation of Silent Loads
Sematic based speculative parallel execution.
The VELOX Transactional Memory Stack
Generating and Comparing Memory Access Ranges for Speculative Throughput Computing
Simple Performance Optimization Techniques for Hardware Transactional Memory Systems
Using Hoarding to Increase the Availability in Shared File Systems
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
Zero-Value Caches: Cancelling Loads that Return Zero.
A Flexible Code-Compression Scheme using Partitioned Look-Up Tables
Cancellation of Loads that Return Zero Using Zero-Value Caches
Zero-Value Caches: Cancelling Loads that Return Zero
Transactions on High-Performance Embedded Architectures and Compilers
Semantic information driven speculative execution
Schemes for avoiding starvation in transactional memory systems
A Flexible Code Compression Scheme using Partitioned Look-Up Tables
Intermediate Checkpointing with Conflicting Access Prediction in Transactional Memory Systems
Efficient Management of Speculative Data in Hardware Transactional Memory Systems
Memory Link Compression Schemes: A Value Locality Perspective
A Micro-Architectural Power-Saving Technique for D-NUCA Caches
Early Detection and Bypassing of Trivial Operations to Improve Energy Efficiency of Processors
Simple Penalty-Sensitive Cache Replacement Policies
Leveraging data promotion for low power D-NUCA caches
Accommodation of the Bandwidth of Large Cache Blocks using Cache/Memory Link Compression
Proceedings of the 14th IEEE Symp. on High-Performance Computer Architecture
Reducing Roll-back Overhead in Transactional Memory Systems by Checkpointing Conflicting Accesses
The worst-case execution-time problem - overview of methods and survey of tools
Zero Loads: Canceling Load Requests by Tracking Zero Values
Implicit Transactional Memory in Kilo-Instruction Processors
Loop-Level Speculative Parallelism in Embedded Applications.
Starvation-Free Transactional Memory System Protocols.
An Adaptive Shared/Private NUCA Cache Partiotioning Scheme for Chip Multiprocessors
Effectiveness of Caching in a Distributed Digital Library.
Improving Power Efficiency of D-NUCA Caches
Characterization of Apache web server with Specweb2005
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
Efficient Management of Speculative Data in Hardware Transactional Memory Systems
Intermediate Checkpointing with Conflicting Access Prediction in Transactional Memory Systems
Proceedings of the 2007 International Conference on HiPEAC
Starvation-Free Commit Arbitration Policies for Transactional Memory Systems.
SimWattch: Integrating complete-system and user-level performance and power simulators
Limits on Thread-Level Speculative Parallelism in Embedded Applications
The Paradigm Shift to Multi-Cores: Opportunities and Challenges
Exposed Datapath for Efficient Computing
Proceedings of the 2007 ACM International Conference on Computing Frontiers
High-Performance Embedded Architecture and Compilation Roadmap
Value-Cache Based Compression Schemes for Multiprocessors
Enhancing Lower Level Cache Performance by Early Miss Determination and Bypassing.
A Cache Replacement Algorithm based on Frequency and Recency for Chip Multiprocessors.
Starvation-Free Commit Arbitration Policies for Transactional Memory Systems.
A Cache-Partition Aware Replacement Policy for Chip Multiprocessors.
Exploitation of Value Locality for Memory Link Compression
Two Threads in the Machine is Better than Eight in the Bush
Exposed Datapath for Efficient Computing
Penalty-Sensitive Replacement Policies for Caches.
A Cost-Effective Memory Organization for Future Servers
Keynote 2: The chip-multiprocessing paradigm shift: Opportunities and challenges
Evaluation of Extended Dictionary-Based Static Code Compression Techniques
Implementing Kilo-Instruction Multiprocessors
Enhancing Simulation Speed using Matched-Pair Comparison
Reducing Misspeculation Overhead for Module-Level Speculative Execution
A Cache Block Reuse Prediction Scheme
Self-Correcting LRU Replacement Policies.
Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores
Improving Speculative Thread-Level Parallelism Through Module Run-Length Prediction
SimWattch: An Approach to Integrate Complete-System with User-Level Performance/Power Simulators
FlexSoC: Combining Flexibility and Efficiency in SoC Designs
Speculative Lock Reordering: Optimistic Out-of-Order Execution of Critical Sections
Reducing Misspeculation Overhead for Module-Level Speculative Execution
Evaluation of Document Prefetching in a Distributed Digital Library.
An Evaluation of Document Prefetching in a Distributed Digital Library
An Evaluation of Document Prefetching in a Distributed Digital Library
Coherence Predictor Cache: A Resource Efficient Coherence Message Prediction Infrastructure.
A Novel Approach to Cache Block Reuse Prediction
An All-Software Thread-Level Data Dependence Speculation System for Multiprocessors
The FAB Predictor: Using Fourier Analysis to Predict the Outcome of a Conditional Branch
Improvement of energy-efficiency in off-chip caches by selective prefetching
TLB and Snoop Energy-Reduction using Virtual Caches for Low-Power Chip-Multiprocessors
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Showing 19 research projects
Pilot using Independent Local & Open Technologies (The European PILOT)
Principer för beräknande minnesenheter (PRIDE)
eProcessor: European, extendable, energy- efficient, extreme-scale, extensible, Processor Ecosystem
PRIME: Principled Designs of Processing-in-Memory Parallel Systems
High Performance Embedded Architecture and Compilation
The European Processor Initiative (EPI)
High Performance and Embedded Architecture and Compilation (HiPEAC5)
TEchnology TRAnsfer via Multinational Application eXperiments (TETRAMAX)
High Performance and Embedded Architecture and Compilation (HiPEAC4)
ACE: Approximate Algorithms and Computing Systems
Meeting Challenges in Computer Architecture (MECCA)
Green Computing Node for European micro-servers (EUROSERVER)
A Framework for Fine-Grain Resource Management in Heterogeneous Parallel Architectures
High Performance and Embedded Architecture and Compilation (HiPEAC)