Per Larsson-Edefors
Visar 177 publikationer
Real-Time Monitoring of Cable Break in a Live Network using a Coherent Transceiver Prototype
Circuit Implementation of Pilot-Based Dynamic MIMO Equalization for Coupled-Core Fibers
Real-Time Implementation of Machine-Learning DSP
Field Trial of FPGA-Based Real-Time Sensing Transceiver over 524km of Live Aerial Fiber
Fiber-on-Chip: Digital Emulation of Channel Impairments for Real-Time DSP Evaluation
FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training
Integration of BCH Encoder in SiGe Driver System
Continuous Fiber Sensing over Field-Deployed Metro Link using Real-Time Coherent Transceiver and DAS
Transoceanic Phase and Polarization Fiber Sensing Using Real-Time Coherent Transceiver
FPGA-based Optical Kerr Effect Emulator
Waveform Memory for Real-Time FPGA Test of Fiber-Optic Receiver DSPs
Fiber-on-Chip: Digital FPGA Emulation of Channel Impairments for Real-Time Evaluation of DSP
Real-Time Transmission over 2x55 km All 7-Core Coupled-Core Multi-Core Fiber Link
Real-Time MIMO Transmission over Field-Deployed Coupled-Core Multi-Core Fibers
Energy-Efficient Implementation of Carrier Phase Recovery for Higher-Order Modulation Formats
Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder
Multi-Format Carrier Phase Recovery Using a Programmable Circuit
Digital Emulation of Time-Varying PMD for Real-Time DSP Evaluations
Benchmarking of Carrier Phase Recovery Circuits for M-QAM Coherent Systems
ASIC Design Exploration for DSP and FEC of 400-Gbit/s Coherent Data-Center Interconnect Receivers
Benefit of Prime Factor FFTs in Fully Parallel 60 GBaud CDC Filters
Challenges and Trade-offs in Real-Time Implementation of DSP for Coherent Transmission
VLSI Implementations of Carrier Phase Recovery Algorithms for M-QAM Fiber-Optic Systems
Power-Efficient ASIC Implementation of DSP Algorithms for Coherent Optical Communication
Implementation of FEC for High-Throughput Optical Communication
Cycle-Slip Rate Analysis of Blind Phase Search DSP Circuit Implementations
Considerations on the Use of Digital Signal Processing in Future Optical Access Networks
Energy-Efficient Soft-Assisted Product Decoders
Towards FPGA Emulation of Fiber-Optic Channels for Deep-BER Evaluation of DSP Implementations
Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-Adaptive Optical Communication
Hardware considerations for selection networks
ASIC Design Exploration of Phase Recovery Algorithms for M-QAM Fiber-Optic Systems
Energy-Efficient High-Throughput VLSI Architectures for Product-Like Codes
ASIC Implementation of Time-Domain Digital Back Propagation for Coherent Receivers
Energy-Efficient High-Throughput Staircase Decoders
A Framework for a Relative Real-Time Tracking System Based on Ultra-Wideband Technology
Power Consumption Savings Through Joint Carrier Recovery for Spectral and Spatial Superchannels
A High-Throughput Low-Power Soft Bit-Flipping LDPC Decoder in 28 nm FD-SOI
Correlators for Interferometric Radiometry in Remote Sensing Applications, A Scaling Perspective
Implementation Challenges for Energy-Efficient Error Correction in Optical Communication Systems
Custom versus Cell-Based ASIC Design for Many-Channel Correlators
Filter Implementation for Power-Efficient Chromatic Dispersion Compensation
Power dissipation issues related to DSP and FEC
Improved Low-Power LDPC FEC for Coherent Optical Systems
CREEP: Chalmers RTL-based Energy Evaluation of Pipelines
Time-Domain Digital Back Propagation: Algorithm and Finite-Precision Implementation Aspects
Data filter cache designs for enhancing energy efficiency and performance in computing systems
Systems and methods for improving processor efficiency through caching
A 3-GHz Reconfigurable 2/3-Level 96/48-Channel Cross-Correlator for Synthetic Aperture Radiometry
Low-Power Low-Latency BCH Decoders for Energy-Efficient Optical Interconnects
Instruction level energy model for the Adapteva Epiphany multi-core processor
Dynamic Equalizer Power Dissipation Optimization
Practical Way Halting by Speculatively Accessing Halt Tags
Low-Power 400-Gbps Soft-Decision LDPC FEC for Optical Transport Networks
Redesigning a tagless access buffer to require minimal ISA changes
Power Consumption of a Minimal-DSP Coherent Link with a Polarization Multiplexed Pilot-Tone
Logic Filter Cache for Wide-VDD-Range Processors
Dispersion Compensation FIR Filter with Improved Robustness to Coefficient Quantization Errors
Energy-Efficient Soft-Decision LDPC FEC for Long-Haul Optical Communication
Exploring early and late ALUs for single-issue in-order pipelines
Power-Efficient Time-Domain Dispersion Compensation Using Optimized FIR Filter Implementation
Improving Data Access Efficiency by Using Context-Aware Loads and Stores
Dispersion Compensation Filter Design Optimized for Robustness and Power Efficiency
Impact of Forward Error Correction on Energy Consumption of VCSEL-based Transmitters
Timing- and power-driven ALU design training using spreadsheet-based arithmetic exploration
MIDAS: Model for IP-inclusive DFM assessment of system manufacturability
Reducing set-associative L1 data cache energy by early load data dependence detection (ELD3)
Assessing Scrubbing Techniques for Xilinx SRAM-based FPGAs in Space Applications
Evaluating Branch Predictor Configurations for a MIPS-like Pipeline
1.6 GHz Low-Power Cross-Correlator System Enabling Geostationary Earth Orbit Aperture Synthesis
Exploring prefix-tree adders using excel spreadsheets
Manufacturable Nanometer Designs using Standard Cells with Regular Layout
Improving Data Access Efficiency by Using a Tagless Access Buffer (TAB)
Towards a Performance- and Energy-Efficient Data Filter Cache
Designing a Practical Data Filter Cache to Improve Both Energy Efficiency and Performance
FlexCore: Implementing an Exposed Datapath Processor
Methodology for Power-Aware Coherent Receiver Design
Speculative Tag Access for Reduced Energy Dissipation in Set-Associative L1 Data Caches
Development of a Cross-Correlator System for Space-Borne Earth Observation Interferometric Imaging
A SiGe 8-Channel Comparator for Application in a Synthetic Aperture Radiometer
Viterbi Accelerator for Embedded Processor Datapaths
Configurable RTL Model for Level-1 Caches
Feasibility Study of FPGA-Based Equalizer for 112-Gbit/s Optical Fiber Receivers
Data-Width-Driven Power Gating of Integer Arithmetic Circuits
Training Design Methodology Skills at the Master’s Level
On Regularity and Integrated DFM Metrics
Application of an Eight-Channel Comparator in a Cross-Correlator for Synthetic Aperture Radiometry
Reconfigurable Instruction Decoding for a Wide-Control-Word Processor
Declarative, SAT-solver-based Scheduling for an Embedded Architecture with a Flexible Datapath
FlexDEF: Development Framework for Processor Architecture Implementation and Evaluation
A SAT-Based Compiler for FlexCore
Power Gating Multiplier of Embedded Processor Datapath
Extracting Vectors from Application Traces for Power Integrity Analysis
3.6-GHz 0.2-mW/ch/GHz 65-nm Cross-Correlator for Synthetic Aperture Radiometry
Application-Specific Energy Optimization of General-Purpose Datapath Interconnect
Design Space Exploration for an Embedded Processor with Flexible Datapath Interconnect
Impact of Standard Cell Pin Placement on Routing Regularity of HPM Architectures
Accelerating Cyclic Redundancy Checking (CRC) Computation in the FlexCore Processor
Digital Cross-Correlators: Two Approaches
Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor
Teaching Bachelors Electronic Circuits with Electronic Systems Design in Mind
Datapath Interconnect Optimization Engine for Energy-Efficient FlexCore Configurations
On-chip power supply noise and its implications on timing
Generation and Exploration of Layouts for Area-Efficient Barrel Shifters
A Single-Chip 64 Input Low Power High Speed Cross-Correlator for Space Application
On-chip Power Supply Noise and Its Implications on Timing
FlexTools: Design Space Exploration Tool Chain from C to Physical Implementation
Supply Voltage Drop Study Considering On-Chip Self Inductance of a 32-bit Processor's Power Grid
Multiplication Acceleration through Twin Precision
Fast Layout Exploration Using the Wired System
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
Towards Supply-Grid-Based Derating of Timing Margins
High-Performance 64-input Cross-Correlator
Double Throughput Multiply-Accumulate Unit for FlexCore Processor Enhancements
Scheduling for an Embedded Architecture with a Flexible Datapath
High-Speed, Energy-Efficient 2-Cycle Multiply-Accumulate Architecture
Custom Layout Strategy for Rectangle-Shaped Log-Depth Multiplier Reduction Tree
Design-Time Scheduling for Processor Exploration
Ultra-Low-Power 2-Cycle Multiply-Accumulate Architecture
Layout Exploration of Geometrically Accurate Arithmetic Circuits
3D chip stacking using planarized carbon nanotubes as through-silicon-vias
High-Speed and Low-Power Multipliers Using the Baugh-Wooley Algorithm and HPM Reduction Tree
Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach
Noise Interaction Between Power Distribution Grids and Substrate
A New Bachelor-Level Electronic Circuits Course at Chalmers University of Technology
Time-Domain Interconnect Characterisation Flow for Appropriate Model Segmentation
Double Throughput MAC for Performance Enhancement of the FlexCore Processor
A New Master's Program in Integrated Electronic System Design
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays
A Flexible Datapath Interconnect for Embedded Applications
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
Toward a Systematic Sensitivity Analysis of On-Chip Power Grids Using Factor Analysis
Overdrive Power-Gating Techniques for Total Power Minimization
Current Probing Methodology for Static Power Extraction in Sub-90nm CMOS Circuits
Exposed Datapath for Efficient Computing
An Efficient FFT Engine Based on Twin-Precision Computation
Multiplier Reduction Tree with Logarithmic Logic Depth and Regular Connectivity
Architecture-Level Power Estimation and Scaling Trends for SRAM Arrays
Exposed Datapath for Efficient Computing
Interconnect Characterization Flow for Minimal-Segment Model Selection
Accounting for the Skin Effect during Repeater Insertion
A Power-Efficient and Versatile Modified-Booth Multiplier
A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating
Fast Dual-Rail Dynamic Logic Style
Table Based Total Power Consumption Estimation Approach for Architects
Evaluation of Power Cut-Off Techniques in the Presence of Gate Leakage
A Power Cut-Off Technique for Gate Leakage Suppression
Glitch-Conscious Low-Power Design of Arithmetic Circuits
Dynamic Pass-Transistor Dot Operators for Efficient Parallel-Prefix Adders
Table-Based Total Power Consumption Estimation of Memory Arrays for Architects
Frequency-Dependent Effects in RLC Interconnects
An Efficient Twin-Precision Multiplier
On Maximum Current Estimation in CMOS Digital Circuits
On Skin Effect in On-Chip Interconnects
Flash [II] - Domino: A Fast Dual-Rail Dynamic Logic Style
A Gate Leakage Reduction Strategy for Future CMOS Circuits
Models for Power Consumption Estimation in the DSP-PP Simulator
DSP-PP: A Simulator/Estimator of Power consumption and Performance for Parallel DSP Architectures
An Investigation of Gate Leakage for Future CMOS Circuits
A Mixed-Mode Delay-Locked Loop Architecture
Full-Custom vs. Standard-Cell Design Flow - An Adder Case Study
FlexSoC: Combining Flexibility and Efficiency in SoC Designs
Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects
Characterizing Ripple-Carry Circuits Using Logical Effort
On Maximum Current Estimation in CMOS Digital Circuits
Full-Custom vs. Standard-Cell Based Design – An Adder Comparison
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Energieffektiv optisk fiberkommunikation